One or more embodiments relate to semiconductor devices and integrated circuits, and to devices for electrical contacting for testing semiconductor devices and integrated circuits.
The term semiconductor devices means in general integrated circuits or chips, respectively, as well as single semiconductors such as, for instance, analog or digital circuits or single semiconductors, as well as semiconductor memory devices such as, for instance, functional memory devices (PLAs, PALs etc.), and table memory devices (ROMs or RAMs, for example, SRAMs or DRAMs).
For the common manufacturing of a plurality of semiconductor devices such as, for instance, integrated circuits, thin discs of monocrystalline silicon are used, which are referred to as wafers in technical language. In the course of the manufacturing process, the wafers are subject to a plurality of coating, exposure, etching, diffusion, and implantation processing, etc. so as to implement the circuits of the devices on the wafer. Subsequently, the devices implemented on the wafer may be separated from each other, for instance, by sawing, scratching, or breaking. After processing is finished, the semiconductor devices are individualized in that the wafer is sawn apart, or scratched and broken, so that the individual semiconductor devices are then available for further processing.
After performing the above-mentioned wafer processing, the devices implemented on the wafer may, for instance, be tested in wafer tests by using appropriate test devices. After the sawing apart or the scratching and breaking, respectively, of the wafer, the chips that are then available individually are molded in a plastics mass, wherein the semiconductor devices obtain specific packages such as, for instance, TSOP or FBGA packages, etc. The devices are equipped with contact faces in the form of contact pads by which the circuits of the semiconductor device can be contacted electrically. During the molding of the chips in the plastics mass, these contact faces or contact pads are connected with external connection pins or contact balls via bonding wires (bonding).
As mentioned above, semiconductor devices are usually subject to comprehensive tests for examining their functions in the course of the manufacturing process in the semi-finished and/or finished state even prior to being molded or incorporated in corresponding semiconductor modules. By using appropriate test systems or test cells, it is also possible to perform test methods on waver level even prior to the individualization of the semiconductor devices so as to be able to examine the operability of the individual semiconductor devices still on the wafer prior to their further processing.
One embodiment serves, for example, to be used in a device for contacting semiconductor devices during the testing of the operability of semiconductor devices with appropriate test systems. In the following, a conventional device for contacting semiconductor devices for test purposes is described.
In order to electrically connect the semiconductor device to be tested in a test station with the test system, a specific contact device, a semiconductor device test card or else probe card is used. At the probe card, needle-shaped connections (contact needles or probes) are provided which contact the electrical connections, connection pins or contact pads, of the semiconductor devices to be tested.
By using the probe card, electrical signals are generated by the test system connected with the probe card at a test station for testing semiconductor devices that are still available on the wafer, and are introduced into the respective contact pads of the semiconductor devices by using the contact needles or contact tips provided at the probe card. The signals output by the semiconductor device at corresponding contact pads in reaction to the input test signals are in turn tapped by the needle-shaped connections or contact tips of the probe card and transferred to the test system, for instance, via a signal line, where an evaluation of the signals may take place.
At the beginning of the process of testing the operability of the semiconductor device, the contact needles or the probe card, respectively, of the test device are usually positioned above the semiconductor device to be tested such that the respectively desired connections or contact needles of the probe card each contact the desired connections or contact pads of the semiconductor device to be tested.
An important precondition for the exact performing of a test method is the reliable contacting of the semiconductor device to be tested with the probe card. To this end, a good electrical connection must be ensured between the contact needles (at the probe card) of the test system and the contact pads of the semiconductor device to be tested.
In the case of high-parallel probe cards, the concept of joint tester channels is frequently used, i.e. that a plurality of chips to be tested or a plurality of contact pads of the chips to be tested are connected with the test system via a tester channel. If only one of the chips tested generates a short circuit on the joint tester channel of the test system, this may also impair the remaining chips tested, even if they do not include any errors. Thus, the effective chips cannot be differentiated from a defective chip, which may result in a yield reduction.
Another problem consists in that high electrical currents are generated by the short circuit generated on the joint tester channel, which are introduced via the contact tips of the corresponding tester channel into the chips connected thereto. Thus, the remaining circuits that are connected to a joint tester channel along with the defective circuit may be damaged. This may also result in a yield reduction and in irreversible damage of the chips tested. There is further the possibility that the contact tip of the needle is damaged by too high a current density, for instance, by melting off the needle tip.
These problems related with the concept of joint tester channels have so far been solved by the involvement of an ohmic resistance with several 100 Ohm in every joint tester channel so as to restrict the currents generated by a short circuit and to thus minimize its effect on the remaining chips that are connected to a joint tester channel along with a defective chip. An aspect of this method consists in that a loss in performance is related with the involvement of the high-ohmic resistance, which impairs the transmission of high-frequency signals, e.g., over 250 MHz. Another aspect of this conventional method consists in that no high-ohmic resistance can be used in the electrical lines for the supply of chip supply voltages that are used for supporting the internal chip voltages since this would result in unacceptable voltage losses in the supply voltage line.
For these and other reasons, there exists a need for the present invention.